1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof.
2. Background Art
In transistors having a MIS (Metal Insulator Semiconductor) structure, miniaturization of gate electrodes has been progressing. In contrast, in order to prevent an increase in contact resistance which is accompanied by reduction in contact area caused in association with misalignment between the gate electrodes and the contact holes, gate contact regions of the gate electrodes in which contacts for the gate electrodes are formed should be formed larger than regions of the gate electrodes which are located on the active region.
FIG. 35 shows a part of a general transistor layout.
As shown in FIG. 35, an isolation region 12 and active regions 13 surrounded by the isolation region 12 are formed in a semiconductor substrate 11, wherein source/drain regions 14 are formed in the upper parts of each active region 13 in general. Gate electrodes 15 are formed across the isolation region 12 and the active regions 13 and include a gate contact region 17 or a wiring region 18. A contact 16 passing through an interlayer insulating film (not shown) is formed in each predetermined region of the source/drain regions 14 and the gate electrodes 15. The line width of the gate electrodes 15 is larger in the gate contact region 17 and the wiring region 18 than on the active region 14. In other words, as shown in FIG. 35, the gate electrodes 15 have forms having line widths changing so as to form rectangular parts in the vicinity of the active regions 13 on the isolation region 12.
Description will be given below to a corner rounding phenomenon caused due to the aforementioned change in line width of the gate electrodes 15 and problems involved by this phenomenon.
In general, the gate electrodes are formed in such a manner that coherent light is irradiated to a photosensitive material called a resist above a semiconductor substrate through a photomask made of a mask-patterned shielding material on a glass substrate so that diffracted light passing through the photomask is one-to-one projected or reduction-projected through a projection lens.
Since transfer of the mask pattern to the resist utilizes optical characteristics of the projected light, the resultant resist pattern deforms and the optical image curves in the vicinity of a part where the line width changes in the presence of interference of the projected diffracted light, as shown in FIG. 36A. Thus, a generally called corner rounding phenomenon occurs in which the rectangle shape of the resist pattern contour 20 is degraded at parts of the mask pattern which correspond to the rectangular parts of the gate electrodes 15 in the vicinity of the active regions 13. The resist pattern contour 20 forms a line width L2 of a part in the vicinity of the boundary between the active region 13 and the gate contact region 17 which is larger than a line width L1 of the other part on the active region 13, as shown in FIG. 36A. As well, the resist pattern contour 20 forms a line width L4 of a part in the vicinity of the boundary between the active region 13 and the wiring region 18 which is larger than a line width L3 of the other part on the active region 13. Accordingly, the gate electrodes 15 formed along the resist pattern contour 20 have line widths (L2 and L4) in the vicinities of the gate contact region 17 and the wiring region 18 on the active regions 13 and line widths (L1 and L3), which are smaller than the line widths (L2, L4), in the other part of the gate electrodes 15 on the active regions 13. This degrades the transistor characteristics to lower the driving power, thereby causing deficiency in circuit operation.
Further, as shown in FIG. 36B, in the case where gate electrodes 5 having the gate contact regions 17, for example, are adjacent to each other, interference of the projected diffracted light lowers the light intensity to cause shortage of resist resolution, so that the adjacent gate electrodes 15 formed are in contact with each other to be short-circuited.
In order to solve the above problems, various methods may be considered, such as a method in which the rectangular parts of the gate contact region and the like or a region having a line width different from the active regions 13 are arranged far away from the active regions 13, a method in which adjacent gate contact regions 17 are arranged apart from each other, and the like. These methods, however, invite an increase in chip area, and therefore, another method called OPC (Optical Proximity Effect Correction) has been proposed in which the mask pattern is corrected. Specifically, light interference is estimated in advance, and the mask pattern is corrected by adding or subtracting a part of the transferred optical image where the interference deforms to or from the mask pattern for the purpose of increasing transfer proximity of the mask pattern (see Japanese Patent Application Laid Open Publication No. 2004-93705 and Japanese Patent Application Laid Open Publication No. 2005-114843, for example).
The conventional OPC, however, makes the mask pattern to be complicated, thereby inviting an increase in calculation time period and difficulty in testing the mask pattern. Also, the conventional OPC requires an additional pattern called serif to the mask pattern for the gate contact region and the wiring region for the purpose of obtaining sharp rectangle shapes at the rectangular parts while at the same time requiring decrease in area of the mask pattern for the gate contact region and the wiring region for the purpose of sufficient separation of the gate contact region and the wiring region. It is difficult to satisfy both the requirements.